1. Field of the Invention
This invention relates to a chip size package and a manufacturing method thereof and in particular to improvement in the resistance of the chip size package to moisture.
2. Description of the Related Art
In the case of manufacturing semiconductor devices, elements are built sequentially in a wafer to form IC circuits each having a predetermined function, as well known. In two dimensions, IC circuit formation parts where the IC circuits are formed are placed like a matrix, dicing line parts are provided like a lattice surrounding the IC circuit formation parts, and the IC circuit formation parts are diced along the dicing line parts to form separate semiconductor devices (semiconductor chips). Then, often each semiconductor device (semiconductor chip) is mounted on connection materials of a lead frame, a film carrier, etc., and is sealed with a resin.
However, in recent years, attention has been focused on a method wherein connection materials are formed and sealing is executed before dicing for miniaturization and simplifying packaging. A chip size package (CSP) is available.
The CSP is also described in JP-A-9-64049, for example. FIG. 9 gives an outline of a chip size package 50 disclosed in JP-A-9-64049. A wafer 51 is formed with a desired element area, then is covered on a surface with a passivation film 51P. An opening is made for exposing each metal electrode 52 (for example, a bonding pad) on the top layer and a rewiring layer 53 is formed by a Cu plating method so as to come in contact with the metal electrode 52 via the opening.
A metal post 55 is formed on the surface of the rewiring layer 53, the full face is coated with a seal resin 56, and the metal post 55 exposed from the seal resin 56 is formed with a solder bump or a solder ball 57.
In this state, dicing is performed along dicing line parts 59 to separate the wafer 51 into complete semiconductor chips 50.
However, the interfaces each between interlayer insulating films deposited in the semiconductor device are exposed to the flanks of the dicing lines. The interfaces become entry passages of moisture, causing malfunction of the IC circuit and destruction of the IC circuit.
Particularly, a number of interlayer insulating films such as a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film are provided depending on the number of layers of metal wiring and moreover each interlayer insulating film is formed by repeatedly depositing films each consisting of a plurality of layers, such as TEOS films or SOG films, considering distortion and flatness. The interfaces each between the films are exposed to the flanks formed in the dicing line parts, causing moisture resistance to be degraded.
A structure wherein the CSP of the rewiring type has a surface coated with a seal resin is also available. It is called seal resin type and is a structure with a surface coated with a seal resin, like that of a conventional package, wherein a metal post is formed on a wiring layer on the chip surface and is surrounded by seal resin for fixture.
Generally, it is said that if a package is mounted on a printed wiring board, a stress generated because of the thermal expansion difference between the package and the printed wiring board concentrates on a metal post; however, in the wafer CSP of the seal resin type, it is considered that the stress is scattered because the metal post lengthens.
The seal resin type provides high reliability by lengthening the metal post about 100 .mu.m and reinforcing the metal post with a seal resin. However, the seal resin foration process needs to be executed using a metal mold at a later step, leading to a complicated process.
On the other hand, the rewiring type has the advantages that the process is comparatively simple and moreover most steps can be executed in the wafer process. However, the stress needs to be relieved for enhancing the reliability by some method.
FIG. 11 is a drawing provided by omitting the wiring layer 53 in FIG. 10. Al electrode 52 forms an exposed opening formed with at least one layer of barrier metal 58 between the metal post 55 and the Al electrode 52, and the solder ball 57 is formed on the metal post 55.
However, in FIG. 10, the insulating film of the lower layer of the wiring layer 53 is formed subtanially by tracing the asperities on the film of the lower layer intact, thus the wiring layer 53 formed on the whole chip area is formed like the shape reflecting the asperities. Therefore, if the heights of the metal posts 55 are constant, asperities are formed on the full face of the wafer, thus the heights from the rear face of the semiconductor substrate to the metal posts 55 vary.
The semiconductor devices comprising the metal posts thus formed are soldered onto a mount board, such as a print circuit board or a ceramic circuit board. However, since the heights from the semiconductor substrates vary, some semiconductor devices have solder balls electrically connected to the conductive pattern of the mount board, and some don't.
Further, the wafer rear face may be shaved from the trend of miniaturization, in which case the wafer is extremely thin.
Thus, if the wafer is placed on metal mold described with reference to FIGS. 12 and 13, it is broken.
As shown in FIG. 12, after the semiconductor wafer is placed, resin 63 is entered in metal mold 60, 61, 62 and ifs pressurized and fused. Semiconductor chips 51 are placed in the metal mold in a state in which a large number of metal posts 55 are upright, and the resin 63 is pressed by the metal mold and the wafer full face is covered with the resin 63. Numeral 64 denotes a sheet for peeling off from the metal mold.
However, if the metal post heads are all pressed so as to abut the metal mold and the sheet 64, distortion is applied to the wafer, which is then broken. Particularly, dust (metal particles several .mu.m to several ten .mu.m in diameter) may exist on the rear face of the wafer, in which case the wafer is pressed with the metal particles as the supporting points and thus is broken more easily.
Therefore, it is desired to flatten the surface of the wafer.